High speed analog-to-digital converter using cells with back-to-back capacitors for both rough and fine approximation

ABSTRACT

A high conversion speed analog-to-digital converter is constituted by a plurality of comparison cells which in successive steps determine first the four most significant bits of the analog-to-digital conversion and then the least significant bits of the same, having first accomplished the reconversion of the four most significant bits to analog and their subsequent subtraction from the input signal.

.[.DESCRIPTION.]. .Iadd.BACKGROUND AND SUMMARY OF THE INVENTION.Iaddend.

The present invention relates to a high speed analog-to-digitalconverter .Iadd.and to a method for analog-to-digital conversion..Iaddend.

Recent developments in the field of digital .[.techniques for the.]..Iadd.signal .Iaddend.processing .[.of signals.]. have increasedinterest .[.for.]. .Iadd.in .Iaddend.high speed conversion.

In particular.Iadd., .Iaddend.the processing of signals in the videoband creates the need of converters with a .[.band width.]..Iadd.bandwidth of .Iaddend.10-50 Mhz and dynamic range .[.field.]..Iadd.range .Iaddend.of 8 bits.

An integrated approach for a digitization system requires theimplementation, inside the conversion device itself, of severalpreprocessing functions.

In .[.such sector.]. .Iadd.this art, .Iaddend.the use is known of flash(or instantaneous) converters having one or two steps. Inparticular.Iadd., .Iaddend.a single-step flash converter allows the useof conversion speeds of 120 Ms/sec (Megasamples per second) with bipolartechnology and of 20 Ms/sec with CMOS technology. This approach does,however, have some drawbacks in terms of dissipated power, silicon area,.Iadd.and .Iaddend.high capacitative load at input.

Such drawbacks are overcome in part by using flash converters having twoconversion steps. In this case the conversion operation provides for afirst step of rough conversion of the sampled input signal, wherebythere are obtained the four most significant bits of the signal atoutput, and a second step which receives at input a signal equal to thedifference between the sampled input signal and the output signal of thefirst conversion step, reconverted to analog, and .[.operates.]..Iadd.performs .Iaddend.a fine conversion completing the digital outputsignal with the four least significant bits.

The use of such two-step conversion devices unfortunately requiresconversion times which are longer with respect to the use of single-stepconverters. It is in fact necessary to execute two successive flashconversions, .[.reconvert to analog.]. .Iadd.including reconverting.Iaddend.the result of the first conversion operation .Iadd.to analog.Iaddend.and .[.execute.]. .Iadd.executing .Iaddend.a subtraction beforethe second fine conversion step.

The object of the present invention is thus to accomplish ananalog-to-digital converter with a very high conversion speed .[.,.].(.Iadd.e.g. .Iaddend.around 50 Ms/sec in .[.the.]. CMOStechnology).Iadd., .Iaddend.which has low input capacitance, low powerdissipation.Iadd., .Iaddend.and .[.optimization.]. .Iadd.optimal use.Iaddend.of .[.the.]. silicon area .[.used.]..

According to .Iadd.an illustrated embodiment of .Iaddend.theinvention.Iadd.,.Iaddend.such object is accomplished by means of aconverter, characterized in that it comprises a plurality of comparisoncells which in successive steps determine the four most significant bitsof the conversion and then the four least significant bits after themore significant bits have been reconverted to analog and .[.theirsubsequent subtraction.]. .Iadd.then subtracted .Iaddend.from the inputsignal.

In particular.Iadd., .Iaddend.each of said comparison cells isconstituted by a comparator with the input connected to an intermediatebranch point between two condensers in series, .Iadd.the first.Iaddend.one of which is supplied in a first step with an input signal,in a second step with a first reference voltage different for eachcell.Iadd., .Iaddend.and in a third step with a selected referencevoltage equal to that of said first reference voltages whichapproximates said input signal .[.downwards.]. .Iadd.from below.Iaddend.with the highest accuracy, .[.and by a .]. .Iadd.with the.Iaddend.second condenser .[.which is.]. .Iadd.being .Iaddend.groundedduring said first and second steps, .[.while.]. .Iadd.and connected,.Iaddend.during the third step .[.it is connected.]. .Iadd., .Iaddend.toone .[.respective.]. of a plurality of second reference voltages.Iadd.which are .Iaddend.submultiples of said first reference voltage.Iadd.(e.g. Vr'=Vr/16).Iaddend..

In this way the result is obtained that a single group of comparatorsaccomplishes both analog-to-digital conversion operations, .Iadd.as wellas .Iaddend.the operation of intermediate digital-to-analog reconversionof the output signal from the first step of analog-to-digital conversionand .[.that.]. .Iadd.the operation .Iaddend.of subtraction of .[.saidsignal.]. .Iadd.the .Iaddend.reconverted .[.to.]. analog .Iadd.signal.Iaddend.from the input signal, which in normal two-step flashconverters are accomplished by two groups of comparators with adigital-to-analog converter and subtractor connected in between. Therefollow .[.favourable.]. .Iadd.favorable .Iaddend.results especially interms of the speed of conversion, of the use of the silicon area and ofpower dissipation.

These and other features of the present invention shall be made evidentby the following detailed description of an embodiment illustrated as anexample in the enclosed .[.drawing.]. .Iadd.drawings..Iaddend.

BRIEF DESCRIPTION OF THE DRAWINGS

.[.The FIGURE.]. .Iadd.FIG. 1 .Iaddend.is a schematic diagram of thepreferred embodiment of the present invention.

.Iadd.FIG. 2A shows a portion of the circuit of FIG. 1 at a first pointin time, FIG. 2B shows the same circuit at a second point in time, andFIG. 2C shows the same circuit at a third point in time..Iaddend.

.Iadd.DESCRIPTION OF THE PREFERRED EMBODIMENTS.Iaddend.

.Iadd.An embodiment of the invention will now be described. It will beunderstood that implicit in the description of the converter is a methodfor analog-to-digital conversion..Iaddend.

In detail, .Iadd.as shown in FIG. 1, .Iaddend.the converter comprises aplurality of comparison cells .Iadd.CCi, .Iaddend.in particular 15 inthe case comparison is required to be executed in the 8-bit range. Thegeneric comparison cell CCi comprises a comparator Cpi, of the type withone input only and with a digital output whose value depends on thevariations of the input voltage, whose input is connected to anintermediate branch point Ni between two series condensers Ci and Ci',respectively.

The condenser Ci is in turn connected, on one side, to the branch pointNi and on the other side it communicates with a parallel of threedifferent switches S1i, S2i, S3i, respectively, which are closed intemporal succession. In particular the switch S1i connects condenser Cito an input voltage .[.Vi.]. .Iadd.Vin, .Iaddend.the switch S2i connectsthe condenser Ci to a reference voltage Vri forming part of a voltagedivider P constituted by a series of resistances Ri, in the specificcase 16, of equal value connected between a terminal supplying a voltageVr and ground, and switch S3i connects condenser Ci to a .[.supply.]..Iadd.rough-approximation .Iaddend.line L1 which, by means of switchSWi, is connected to .[.that.]. .Iadd.the one voltage Vrx,.Iaddend.among the different reference voltages Vri.Iadd.,.Iaddend.which is in turn selected by a coding logic LC sensitive to theoutputs of comparators Cpi as that which approximates the input voltage.[.Vi.]. .Iadd.Vin .Iaddend..[.downwards.]. .Iadd.from below.Iaddend.with the highest accuracy.

Condenser Ci' is in turn connected, on one side, to the branch point Ni,and on the other side communicates with a parallel .Iadd.combination.Iaddend.of two switches, S1i', S3i', respectively, of which S1i'grounds said condenser C1 and S3i' connects said condenser Ci' to areference voltage Vri' forming part of a voltage divider P' constitutedby a series of resistances Ri', in the specific case 16, of equal valueconnected between a terminal supplying a voltage Vr', where Vr'=Vr/16,and ground.

The input Ii of each comparator is also connected to the respectiveoutput Ui by means of a switch SS1i.

Due to the described structure the analog-to-digital converter operatesas follows.

During a first step, .Iadd.as shown in FIG. 2A, .Iaddend.switches S1iare closed and the value of the input voltage .[.Vi.]. .Iadd.Vin.Iaddend.is .[.,.]. memorized in condensers Ci. Switches SS1i also areclosed to allow automatic cancellation of the offset at the terminals ofcomparator Cpi. During this step, condensers Ci' are grounded throughswitches S1i', closed simultaneously with switches S1i .Iadd.andSS1i..Iaddend.

During a second step, .Iadd.as shown in FIG. 2B, .Iaddend.switches S1i,S1i'.Iadd., .Iaddend.and SS1i are open and switches S2i areclosed.Iadd., .Iaddend.so that the left-hand .[.armature.]. .Iadd.side.Iaddend.of the generic condenser Ci is brought to a respectivereference voltage Vri. As a consequence.Iadd., .Iaddend.while condenserCi still memorizes the input voltage .[.Vi.]. .Iadd.Vin .Iaddend., thevoltage at the branch point Ni changes to a value .[.(Vr-Vi).].(.Iadd.Vri-Vin) .Iaddend.which according to its .[.the.]. .Iadd.its.Iaddend.sign (+or -) .[.translates.]. .Iadd.is translated .Iaddend.to alogic level 0 or 1 on the generic output .[.Vi.]. .Iadd.Ui .Iaddend.ofcomparator Cpi. There is thus .[.operated.]. .Iadd.performed .Iaddend.arough conversion of the input signal .[.obtaining.]. .Iadd.Vin to obtain.Iaddend.(.Iadd.in this example.Iaddend.) the 4 most significant bits ofthe digitalized signal .[.Vi.]..

During a third step .[.with.]. .Iadd., as shown in FIG. 2C,.Iaddend.switches S2i .Iadd.are .Iaddend.returned .[.in.]. .Iadd.to.Iaddend.open condition.Iadd., and .Iaddend.the coding logic LC, havingdetected the logic levels at the outputs of comparators Cpi, commandsthe closing of a selected switch SWi corresponding to the one.Iadd.reference voltage Vrx, of all the .Iaddend.referencevoltage.Iadd.s .Iaddend.Vri.Iadd.,.Iaddend.which best approximates thevalue of the four most significant bits of the input voltage .[.Vidownwards.]. .Iadd.Vin from below, .Iaddend.thereby carrying out areconversion of .[.said.]. .Iadd.the .Iaddend.four most significant bitsinto a corresponding analog signal. Switches S3i and S3i' are thenclosed to connect .Iadd.all of .Iaddend.the condensers Ci to theselected reference voltage (.[.Vrix.].) (.Iadd.Vrx.Iaddend.), and.Iadd.to connect the .Iaddend.condensers Ci' to respective referencevoltage.Iadd.s .Iaddend.Vri'. As a consequence, the branch point Nimoves to a voltage .[.Vi-Vrix.]. .Iadd.Vin-Vrx, .Iaddend.therebysubtracting a voltage corresponding to the analog conversion of the fourmost significant bits of the digital output signal from the inputvoltage .[.Vi.]. .Iadd.Vin. .Iaddend.According to whether .[.Vin-Vrix.]..Iadd.Vin-Vrx .Iaddend..[.;.]. is lower or higher than the referencevoltage Vri', the voltage at .[.the.]. .Iadd.each .Iaddend.branch pointNi translates to a logic level 0 or 1 on the generic output Ui, thusresulting in .[.to.]. a .[."and delete and allows the operation"; andallows the operation.]. fine conversion .Iadd.operation .Iaddend.givingthe 4 least significant bits of the input signal .[.Vi.]..Iadd.Vin.Iaddend..

We claim:
 1. .[.High.]. .Iadd.A high .Iaddend.speed analog-to-digitalconverter, .[.characterized in that it comprises.]. .Iadd.comprising;.Iaddend.a plurality of comparison cells which in successive stepsdetermine the .[.four.]. most significant bits of the conversion andthen.Iadd.,.Iaddend..[.the four least significant bits.]. after the moresignificant bits have been reconverted to analog and .[.their subsequentsubtraction.]. .Iadd.subtracted .Iaddend.from the input signal.Iadd.,the least significant bits;.Iaddend. .[.where.]. .Iadd.wherein.Iaddend.each .[.of.]. said comparison .[.cells is constituted by.]..Iadd.cell comprises .Iaddend. a comparator .[.with.]. .Iadd.having an.Iaddend.input connected to an intermediate branch point between.[.two.]. .Iadd.first and second .Iaddend.condensers in series, .[.oneof which is .]. .Iadd.said first condenser being .Iaddend.supplied in afirst step with an input signal, in a second step with a first referencevoltage different for each cell.Iadd., .Iaddend.and in a third step witha selected reference voltage equal to .[.that.]. .Iadd.the one.Iaddend.of said first reference voltages which approximates said inputsignal .[.downward.]. .Iadd.from below .Iaddend.with the highestaccuracy, .[.and by a.]. .Iadd.said second .Iaddend.condenser .[.whichis.]. .Iadd.being .Iaddend.grounded during said first and secondstep.Iadd.s .Iaddend., .Iadd.and connected, during said.Iaddend..[.while in the.]. third step.Iadd., .Iaddend..[.it isconnected.]. to .Iadd.a respective .Iaddend.one .[.respective.]. of aplurality of second reference voltages .Iadd.which are.Iaddend.submultiples of said first reference voltage. 2..[.Converter.]. .Iadd.A converter .Iaddend.according to .[.Claim.]..Iadd.claim .Iaddend.1, further comprising .[.a.]. decoding logic whichdetects the value of the outputs of said comparators during said secondstep.Iadd.,.Iaddend.and .Iadd.accordingly .Iaddend.determines duringsaid third step the choice of said selected reference voltage..Iadd.3.The converter of claim 1, wherein said comparator is a single-inputcomparator..Iaddend..Iadd.4. The converter of claim 1, furthercomprising a shorting switch connected to short together an input withan output of said comparator during said first step..Iaddend..Iadd.5.The converter of claim 1, comprising 15 of said cells..Iaddend..Iadd.6.An integrated data conversion circuit, comprising:.Iaddend.a pluralityof comparison cells, each includingfirst and second capacitors eachhaving a respective first terminal connected to a common node. athresholding logic circuit connected to provide a digital outputcorresonding to the analog voltage of said common node a firstinitializing switch connected to selectably connect a second terminal ofsaid first capacitor to an analog input voltage, and a secondinitializing switch connected to selectably connect a second terminal ofsaid second capacitor to a constant voltage, a reference-connectingswitch connected to selectably connect said second terminal of saidfirst capacitor to a particular respective correspondingrough-approximation reference voltage, and a first fine-approximationswitch connected to selectably connect said second terminal of saidfirst capacitor to a common rough-approximation line, and a secondfine-approximation switch connected to selectably connect said secondterminal of said second capacitor to a particular respectivecorresponding fine-approximation reference voltage which is smaller inmagnitude than said particular respective correspondingrough-approximation reference voltage; and control logic connected toreceive the outputs of said thresholding logic circuits, and connectedto activate said initializing switches in a first phase, saidreference-connecting switch in a second phase, and saidfine-approximation switches in a third phase, and, during said secondphase, to connect, to said rough-approximation line, one of saidrough-approximation reference voltages which is selected in dependenceon the outputs of said thresholding logic circuits after said firstphase; whereby the outputs of said thresholding logic circuits provide atwo-stage digital output corresponding to said analog inputsignal..Iadd.7. The integrated circuit of claim 6, wherein saidthresholding logic circuit is a single-inputcomparator..Iaddend..Iadd.8. The integrated circuit of claim 6, furthercomprising an additional respective switch between each saidrough-approximation reference voltage and said rough-approximation line,and wherein said control logic is connected to activate a selected oneof said additional switches during said second phase..Iaddend..Iadd. Theintegrated circuit of claim 6, further comprising a first resistorladder which supplies said rough-approximation reference voltages frommultiple nodes thereof, and a second resistor ladder which supplies saidfine-approximation reference voltages from multiple nodesthereof..Iaddend..Iadd.10. The integrated circuit of claim 6, comprisingexactly 15 of said comparison cells..Iaddend..Iadd.11. A method foranalog-to-digital data conversion, comprising:providing a plurality ofcomparison cells, each including first and second capacitors each havinga respective first terminal connected to a common node, and athresholding logic circuit connected to provide a digital outputdependent on the analog voltage of said common node, during a firstphase, connecting an analog input voltage to a second terminal of eachsaid first capacitor, and connecting a second terminal of each saidsecond capacitor to ground; during a second phase, connecting adifferent respective one of a first set of reference voltages to saidsecond terminal of each said first capacitor; selecting arough-approximation voltage in dependence on the outputs of saidthresholding logic at the end of said second phase; and during a thirdphase, connecting said rough-approximation voltage to said secondterminals of all of said first capacitors, and connecting a differentrespective one of a second set of reference voltages to said secondterminal of each said second capacitor; and outputting bitscorresponding to said outputs of said thresholding logic at the end ofsaid second phase as more significant bits, and outputting bitscorresponding to said outputs of said thresholding logic at the end ofsaid third phase as less significant bits, to provide a digital valuecorresponding to said analog input value..Iaddend..Iadd.12. The methodof claim 11, wherein, during said second phase, said second set ofreference voltages provides four bits of additional resolution withrespect to said first reference voltages..Iaddend..Iadd.13. The methodof claim 11, wherein said first set of reference voltages is provided bya first resistor ladder, and said second set of reference voltages isprovided by a second resistor ladder..Iaddend..Iadd.14. The method ofclaim 11, wherein said selecting step is performed by control logicwhich is connected to receive the outputs of each said thresholdinglogic circuit..Iaddend..Iadd.15. The method of claim 11, wherein saidthresholding logic circuit is a single-input comparator..Iaddend.